The present disclosure relates to semiconductor device fabrication, and more specifically, to a self-aligned metal wire on a contact structure and methods of forming the contact structure and metal wire.
Conventional integrated circuit (IC) (i.e., chip) formation generally occurs on the surface of a semiconductor substrate, e.g., silicon wafer. ICs may include a variety of interconnected semiconductor devices such as resistors, transistors, capacitors, etc., formed on the surface of the semiconductor substrate. Due to the large number of devices and complex layout of the ICs, the devices cannot be connected within the same device level. The devices may therefore be interconnected, for example, by a complex wiring system formed in one or more layers above the device level. The wiring system may include, for example, stacked metal containing layers, i.e., metallization layers, which include metal wires providing intra-level electrical connections. The wiring system may also include layers stacked between the metallization layers including vertical structures, i.e., vias for inter-level electrical connections between the metallization.
The wiring system may be electrically connected to the semiconductor devices of the device level by a “device-level” vertical connection structure, i.e., contact structure (CA). The contact structure may be formed in an initial via layer (VO) of the device level which encloses the semiconductor devices. A first end of the contact structure may connect to a respective contact region of a semiconductor structure, e.g., a gate electrode or source and drain region of a transistor. The second end of the contact structure may connect to a respective metal wire in a metallization layer thereabove. The second end of the contact structure may be directly connected to the respective metal wire, or indirectly connected to the respective metal wire by a via.
One challenge associated with connecting the contact structure to the metallization layer may include misalignment of via and/or metal wire with the contact structure therebelow. Turning to the figures, FIG. 1 shows a semiconductor structure 100 including a conventional contact structure 112 in a dielectric layer 114 of a device layer 116. Contact structure 112 is positioned on a trench silicide structure 108 which electrically connects the contact structure to a source and drain region 106 of a fin 104 positioned in a shallow trench isolation (STI) dielectric 110 on a substrate 102. Contact structure 112 is also electrically connected to a conventional metal wire 118 in a dielectric layer 124 of a metallization layer 120 above device layer 116. As shown in FIG. 1, contact structure 112 may include a maximum width W1 of approximately 12 nanometers to approximately 50 nanometers. As shown in FIG. 1, contact structure 112 may include a vertical cross-sectional geometry of a trapezoid wherein an upper surface 126 of the contact structure is wider than a bottom surface 128 of the contact structure. Contact structure 112 may be formed, for example, by directly forming an opening (not labeled) in dielectric layer 114 and forming contact material therein. Although not shown, the conventional opening (not labeled), and therefore contact structure 112, may include a substantially circular, or ellipse top cross-sectional geometry. As shown in FIG. 1, contact structure 112 is misaligned with metal wire 118 at region 122 (in phantom). Misalignment the connections of a wiring system (e.g., conventional metal wire 118) with a conventional contact structure (e.g., contact structure 112) therebelow may result in a weak electrical connection, a higher resistance at the metal wire—contact structure interface, and variation of resistance across multiple metal wire—contact structure interfaces of a semiconductor structure. The misaligned metal wire on the contact structure may also render the semiconductor structure inoperable.